The SMT lab at Universal Instruments, Binghamton, New York, conducts extensive research in Chip Scale Package (CSP) technology, Direct Chip Attach (DCA), and Optoelectronics. The research focuses on all the pertinent issues in material selection, assembly, rework, modeling, and reliability evaluation of CSP and flip chip assemblies. The SMT lab at Universal Instruments consists of industry experts with numerous years of "hands-on" experience and Graduate students (Doctoral and Masters Level) with applied knowledge in the area of CSP/DCA research. The group functions as a team to address industry-relevant issues and provides practical solutions directly applicable in the industry.
[ Chip Scale Package (CSP) Group ]
The main areas of research include the study of High Density Chip Scale Package technology, Stacked CSP technology, High Density Printed Circuit Board (PCB) technology for advanced CSP Packages, Assembly Process Optimization, Rework and Repair of CSPs/BGAs, CSP Underfilling, Codification Software, and Lead-free research. The extensive, "high-tech" laboratory facilities at the SMT Lab at Universal Instruments facilitate the advanced research in CSP/BGA Technology.
High Density Chip Scale Packages
High density CSPs, Stacked Die CSPs, Wafer Level CSPs, Leadless CSPs, Flip Chip BGAs, in both lead-free and tin-lead alloy configurations are extensively studied. The I/O counts range from 4 I/Os to 1517 I/Os with a pitch of 0.5mm to 1.27mm. The Packages are thoroughly characterized with respect to moisture sensivity, component level reliability in aging and ball shear studies, dimensional variations, warpage at various temperatures, and ball coplanarity. Robust assembly and rework processes are developed for each package. The reliability of each package is evaluated in various thermal cycling tests and mechanical tests. The effects of various assembly and design parameters on the consequent reliability of the assembly is systematically researched. Failure analysis provide insight into the many failure modes and aid in defect analysis.
High Density Printed Circuit Boards
With the increasing component density and functionality, high density, multilayered PCBs are becoming commonplace. The research is focused on various microvia technologies, pad design, via-in-pad design considerations, in addition to various surface finishes. Microvia reliability evaluation and also the assembly level reliability of various pad designs and surface finishes are studied.
CSP Underfill
CSP assemblies in mobile applications are typically underfilled to improve the mechanical reliability of the assembly. Extensive mechanical reliability studies are carried out considering various commercial and experimental underfills with various packages. Reworkable underfills, which facilitate rework, are being extensively researched and also the effect of rework on the reliability of the packages is being studied.
CSP Rework
Rework of CSP/BGA packages pose additional challenges owing to the solder joints being hidden underneath the package body. The development of rework processes for the CSP/BGA packages requires careful consideration of the various processes that are involved in the rework of these packages including thermal profiling, component removal, site redressing, solder/flux replenishment, and component replacement. One major problem being addressed here is the operator dependency of the rework operation and research is being conducted to reduce operator interaction/dependency. The effect of rework on the reliability of reworked CSP/BGA assemblies is another major area of research.
Lead-free Solders
As the industry moves towards lead-free electronics, research into lead-free systems is of primary importance. The CSP group conducts a variety of studies addressing lead-free systems. Some of the important studies include solder alloy evaluation, assembly process development for lead-free CSP/BGA components using lead-free solder paste, reliability evaluation of the lead-free systems, alternate lead-free surface finishes, lead-free rework, and failure analysis for lead-free assemblies.
Codification Software
Data of enormous proportions, software development expertise, and an expert systems based approach has resulted in the development of a large database and an expert system that helps the user to explore the various process issues in surface mount assembly. Reliability and yield predictions, warpage calculations, and board routing considerations are some of the features of this software. This software is being constantly updated and newer modules are being incorporated.
[ Direct Chip Attach Group ]
The Direct Chip Attach (DCA) group is actively involved in the process related and reliability issues of flip chip assembly. The flip chip assembly focuses on various issues related to materials and processing methods such as Pb-free assembly and underfilling. The flip chip reliability concerns the understanding of damage and failure mechanisms based on the effects of material properties, interactions, and compatibility. In addition, there is an effort to develop a software that will predict the assembly yield based on the issues of both the assembly and reliability of flip chip.
[ Optoelectronics ]
Optoelectronics, the alliance of optics and electronics, shows increasing applications in the fields of telecommunications and consumer electronics. The work at EMRS has been presently focused on three prominent areas, Optical Fibers, Optical Adhesives, and Gold-Tin solders. Studies on the mechanical properties of optical fibers are being conducted. Evaluation of cure properties and dot dispensing of optical adhesives is being carried out. In addition, properties of Gold-Tin solder with respect to its application in Photonic packaging are being studied.
[ Other Projects @ Universal ]
Programming and Optimization Software
The project offers a consistent methodology to generate an optimal schedule depending on production and set-up data for one or more assembly lines, with any combination of GSM platforms and HSP machines. The project involves developing a schedule to manufacture products over a given period of time. The algorithms used to come with an optimal schedule will involve the use of Earliest Due Date (EDD) heuristic, the Shortest Processing Time (SPT) heuristic and/or a combination of both. The schedule will be designed to satisfy constraints regarding product release due dates, tardiness (lateness) and resource capacity. The project will also involve development of an algorithm to incorporate the introduction of a new product to the schedule to dynamically reschedule production in order to satisfy the constraints listed above. Reduction of set-up times can be achieved by grouping the products into a family of products. An algorithm will be developed to optimize the schedule for a family of products.
Manufacturing Monitoring and Equipment Interface Software
Each piece of equipment in an assembly line provides a user interface responsible for that unit's operation, programming, optimization and data management. However, the machines in that line may lack a common user interface, which makes it difficult for manufacturers to manage their production line efficiently. The Equipment Interface Software creates a single high-level integrated graphical user interface solution across all machines in a line with standard Universal line configurations.
The manufacturing monitoring module provides a single point of storage retrieval for review and analysis of machine management data. It offers web-based browsing, component traceability, remote notification, and performance monitoring. It serves as the internet window to the manufacturing environment. The manufacturing monitoring software includes Visual Basic programs that collect machine events and insert and normalize the raw data into a database. Web enabled clients can view the data and generate reports from the same.
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