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The rapid development of area array packages has placed extraordinary demands on the substrates used to interconnect this new class of components. The trend in portable electronics is towards smaller and lighter products with increased functionality. Increased product functionality coupled with drastic size reduction places extreme demands on the designer to increase silicon integration, reduce silicon package size, and reduce Printed Circuit Board (PCB) size. High Density Interconnect (HDI) technology is the enabling technology for the next generation of small portable electronic communication devices. These methods employ a photoimageable dielectric, a laser ablated dielectric, or a resin coated copper foil with laser, photo or plasma etched via fabrication. In this research, the effect of different factors on the reliability of the microvias was extensively evaluated. The reliability of microvia interconnect structures was evaluated using Liquid-To-Liquid Thermal Shock (LLTS) testing. A significant number of new approaches (via formation technologies) are currently under development in research laboratories, to meet these demands. The microvias were fabricated using different laser ablation and photoablation technologies. Non-glass reinforced and glass reinforced dielectric materials were used. Laser technologies, such as YAG laser drilling and YAG-CO2 laser drilling, were evaluated. Cross-sections were used to evaluate the vias and parameters such as wall inclination, shape, and plating thickness. The resistance of the via chain was measured at various stages of LLTS testing. Samples that failed were subjected to non-destructive and destructive analysis in order to fully understand the failure mechanism. The effect of the proximity of microvias to the PTHs on the fatigue life was studied. The samples were tested for 2000 LLTS cycles. Testing revealed that vias that were located close to the PTHs (<30 mils) showed fewer fails than those at a distance of greater than 30 mils. It is suspected that the local CTE effect of the PTH prevents microvias from debonding. It is proposed that the mechanical interlocking and Z-axis CTE of the copper PTH prevents the high CTE epoxy/glass layers from expanding. This in turn causes local ‘Z?axis constraint on the outer dielectric layer around the PTH, which reduces the occurrence of the main failure mode for microvias which is the separation of via from the stop pad. Therefore, microvias close to PTHs last longer than those located farther away. These results were compared to bare board via reliability test results. This research effort showed that vias (< 4 mils) failed earlier than those with a larger diameter (6 mils and 8 mils). The plating quality of large (6 mils and 8 mils) vias was found to be better than smaller microvias (< 4 mils). Improper plating at the bottom of the via coupled with a high stress concentration resulted in a break at the via pad interface. The uncleaned epoxy and glass fibers in the via hole are significant cause of via failures.


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