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There is an increasing demand for high-performance equipment for applications in the networking and telecommunications industry. The increased speeds of the logic families used in digital electronics and the advances in semiconductor technology are two of the important factors that have provided the scope for the development of improved design solutions. An increase in the logic speeds has transformed Printed Circuit Boards (PCBs) from being the physical carriers of the components of the system, to a critical and integral part of the system's design. The electrical characteristics of the boards constitute an important element on which the functionality of the product depends. The advances in component and packaging technology have enabled the use of large 'ASICs' on the PCBs. The requirement to provide multiple features on smaller and thinner PCBs has increased the component densities on the boards. High Density Interconnect (HDI) PCB fabrication technologies are considered to alleviate the problems that arise from the demand for high speed and high density PCBs. These technologies are being used as alternatives to the conventional board fabrication technology. The drive for higher speed and higher performance on smaller boards has led to an increase in the complexity of PCB design, layout, routing, and fabrication processes. At higher logic speeds, the PCB interconnections behave like transmission lines. The characteristic impedance of transmission lines is a very important source of degradation of signal integrity in high-speed PCB designs, and is affected by various factors. As a part of this research, a 2-Dimensional (2D) field solver model was selected for the prediction of impedance. A test vehicle incorporating different transmission line configurations and structures was designed for fabrication by two vendors. Conclusions were drawn on the vendors' ability to meet the impedance requirements. The results from this test vehicle provided inputs to the field solver for the prediction of impedance. A value for the effective dielectric constant of the material used was also obtained through the measurement of propagation delay. It was concluded that the selected field solver could be used for the prediction of impedance for new PCBs. The use of high I/O area array packages is one of the factors that can affect the number of signal layers required in a PCB. As a part of this research, algorithms were developed to predict the minimum number of signal layers needed to pin-escape different types of high I/O area array packages on PCBs fabricated using conventional and HDI technologies. This established a definite lower limit for the number of signal layers required. Based on the results obtained, software was developed to help the designers predict the required number of signal layers for a given package.


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