Overview
Masters '04
Masters '03
Masters '02
Masters '01
Masters '99
Masters '98
Masters '97
Masters '96
Masters '95
Masters '94
Masters '93
Masters '92
Masters '91
Masters '90
Masters '89
Doctoral '90-'01
alumni

Masters Abstracts (2000)

SITARAMAN, MADAN MOHAN
(August 2000), Member of Technical Staff (MTS), VLSI Technology, Shelton, CT

Email: msitaram@txc.com

Research in the Rework of Lead-Free Area Array Assemblies

With the advent of Chip Scale Packages (CSPs), the electronic manufacturing industry is faced with several challenges, especially, in the rework environment. Some of the challenges include the small size of the component and the solder ball, fine pitch of the components, small pad size, and a high number of Input/Outputs (I/Os). This research effort is focussed on the rework of fine pitch CSPs (less than 0.75 mm pitch). A generic process for the rework of fine pitch packages was developed. A set of CSP assemblies with I/Os ranging from 8 to 328, on a pitch of 0.5 mm, was reworked and is presently undergoing reliability evaluation. To address the issues specific to fine pitch, experiments were also conducted on CSPs with reference to site cleaning, fluxing and replacement to evaluate the different techniques and methodologies. In addition to the conventional CSPs, certain ‘bump-less?CSPs were also reworked using the techniques derived from previous experiments. These bump-less packages needed solder deposition before assembly, and a localized printing process was evaluated to address this issue.

Via-in-pad structures are being increasingly used to cope with higher density and reduced pitch in circuit boards. In these pad structures, vias are drilled on the pad to route it to the next layer. The rework of chip scale packages that are assembled on sites with via-in-pad structures offers several challenges in addition to the fine pitch of the chip scale packages used. One of the challenges is the removal of voids formed during assembly. In this research effort, chip scale packages were assembled using a rework station and then reworked using the conventional rework process. Efforts were made particularly in the component removal and site redressing process to eliminate voids that resulted from the use of via-in-pad structures.

With increasing interest in solders containing no-lead alloys due to environmental considerations, materials and process need to be characterized for surface mount assembly and rework. This study developed a preliminary process for the rework of no-lead BGAs. The various issues and concerns that are pertinent to the individual steps of rework were investigated and recommendations were provided for a suitable process. Higher peak temperatures being the main challenge, the consequence of using correspondingly higher temperatures for the heater settings were studied and solutions provided to avoid some of these problems. Components were reworked and then subjected to reliability testing to compare their lifetime with conventional eutectic tin-lead alloys on the same component.

 

 
sitemap | contact us