Masters Abstracts (1998)

GOPALAKRISHNAN, LAVANYA
(May 1998), Manufacturing Engineer, Cyras, Fremont, CA

Email: lavanyag@cyras.com

Process Planning For Ultrafine Pitch and Area Array Surface Mount Assembly

The parameters that affect the stencil printing process were evaluated in order to develop a fundamental understanding of the complex interactions between them. Multiple experiments were carried out using a 'design of experiments' based approach. The components considered varied from 12 mil pitch ultrafine pitch devices to large I/O BGAS. Comprehensive statistical analysis was performed and 'optimal' material and process parameters were identified. Response surface methodology was used to identify the process windows for solder paste deposition. A robust BGA assembly process with no process induced defects was developed. The knowledge gained in this research was combined with information gathered from a variety of sources to develop a computer aided process planning system. This process planning system allows the user to systematically determine the methods and the process parameters by which PCBs can be populated with ultrafine pitch and BGA components.