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One of the main thrusts in the electronics packaging and assembly industry today, is the continual increase in circuit density and functionality per unit area, at the semiconductor (die) level and consequently for the board interconnection level. The drive towards finer, denser and more complex components, is merely a consequence of this. In the broad sense of the surface mount arena, it can be said that components with peripheral architecture may no longer meet the present day requirements, and are being gradually replaced by area array architecture devices like the Ball Grid Array (BGA). BGA technology has developed into the package of choice. The Chip Scale Package (CSP), which is presently undergoing a tremendous amount of research, can be considered to be a further development of the BGA technology. Due to their leadless configuration, larger ball pitch, and compatibility with existing surface mount PCB assembly equipment, BGAs avoid a significant segment of the assembly problems encountered in fine pitch assembly. The recent explosive growth in BGA/CSP development has been fueled by the promise of exceptionally high yields. Through intense research in the field of BGA and CSP devices, most of the problems associated with these assemblies have been overcome, yet, successful assembly can only be obtained through superior process control. Although BGAs have been in use for the past few years, they are a relatively new technology, especially for the contract assembly arena. A majority of the BGA packages currently being used have a standard nominal pitch of 1.27 mm. As the pitch drops, particularly below 0.8 mm, (which is quite common for a number of CSPs), the CSPs cross the realm of traditional BGAs presenting challenges as well as opportunities for process development. When coupled with the contract-manufacturing environment, these challenges assume considerable importance. Process development is one of the key steps for the successful implementation of new technologies. During this stage, many innovative and creative ideas, techniques and methods are investigated. The present research effort concentrated on implementing new technology, gaining experience in assembly of advanced packages, and assimilating all the relevant information through experimentation. Each step of the assembly process was considered in process development, starting with card design, printing optimization, and finally the assembly process. A test vehicle was successfully designed in-house for the purpose of developing a fundamental understanding of the complex interactions involved in the high volume production of area array assemblies while concurrently developing a high-yield process for a variety of BGA and CSP components using existing surface mount equipment. This test vehicle also served as a tool in making the engineers at an EMS provider's facility aware of the formalities associated with establishing imminent, advanced technologies like high-interconnect area array devices, intrusive soldering, microvia technology, and the assembly of Printed Circuit Boards (PCBs) that have BGAs/CSPs on both sides. Microvia technology has been successfully (though at an elementary level) integrated on to the test vehicle. The no-clean stencil printing process was studied and characterized for diverse, advanced surface mount packages. Additionally, printing was characterized for a Through-Hole Component (THC) which was to be reflow-soldered along with the area array components. The challenge was to identify a single stencil thickness and paste type for a diverse range of solder volumes with approximately 130,000 cubic mils of solder paste for the THC (with adequate hole-fill) at one extreme and at least 800 cubic mils for the mBGA at the other. Multiple experiments were carried out using a Design of Experiments (DOE) based approach. Three different stencil thicknesses, two types of paste, and three different aperture shapes were studied to identify the optimal materials for the overall system. Further experiments were conducted to establish a comparison between the print performances of a metal and a polyurethane squeegee. Comprehensive statistical analysis was performed to establish the findings from these experiments. The culmination of this systematic, step-by-step approach involved the final assembly of the test vehicle. The success of the final assembly authenticated the correctness of the test vehicle design, the parameters obtained from the optimization of the stencil printing process, as well as precision of the reflow profiling methodology. Overall 336 (176 single sided and 160 double-sided) area array components with 100128 (52448 single sided and 47860 double-sided) solder joints were assembled and a 100 % X-ray inspection showed that there were no cases of solder bridging or component mis-alignment. Solder joint quality was further confirmed by conducting cross-sectional analysis of representative samples. Recommendations have been made for obtaining special placement and inspection equipment to provide the additional flexibility required for the successful assembly of area array devices in high volumes. Succinctly put, this research was successful in developing an 'approach' to facilitate/smoothen the transfer of SMT and related technologies for the assembly of advanced semiconductor packages, from the developmental level to controlled implementation in production.


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