Masters Abstracts (1999)

PATEL, PARVEZ
(December 1999), Motorola, AMST Group, Libertyville, IL

Email: Parvez.patel@motorola.com

Assembly process development for Ball Grid Array and Chip Scale Package on high density interconnect

This research effort has explored an expansive range of issues, including those in board evaluation, board design, and several material and process factors that affect various sub-processes in the assembly of Ball Grid Arrays (BGAs) and Chip Scale Packages (CSPs) on High Density Interconnect (HDI) substrates. The research effort first looked at bare board issues that relate to HDI substrates, particularly the via-in-pad, dog-bone, and conventional pad structures. The aim was to focus on the bare board factors related to the assembly and reliability of the packages. Thorough characterization of the test board, accompanied by statistical analysis revealed factors such as via shape, pad-via offsets, plating quality, and via formation technologies that could have a significant bearing on the assembly process yield and subsequent product reliability. A large variation in the board features, dependent on the board vendor and technology, was observed. Eight assembly builds were performed to study assembly, material, and process parameters for the attachment of BGAs and CSPs to the test boards. Emphasis was placed on the identification of parameters and the assembly process windows. More than 1200 area array components were assembled, of which 10 were found to be defective. These defects and assembly failures shed light on important issues that need to be addressed. These, among others, include component warpage, insufficient fluxing, bump coplanarity, improper adhesion of the via to the capture pad, and card warpage. It also brought into focus the issue of void formation in the via-in-pad solder joints. Subsequently, the research concentrated on studying the mechanism of void formation in the via-in-pad solder joint. The elimination of voiding by offset printing helped conclude that improper of filling of the via during the solder paste deposition process resulted in the void formation. A case study on the assembly and reliability of a wafer level CSP on the via-in-pad structure is presented. Several factors, including the affect of pad size, solder paste and flux and the effect of the via-in-pad structure on the solder joint reliability, were studied. It was concluded that the solder joints on the via-in-pad structure were as reliable as those on a conventional pad. Finally, based on the process development effort, a comprehensive process 'cook-book'/overview that addresses the concerns that relate to the assembly of BGAs and CSPs on HDI substrates is presented.